A 1.8 v 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

摘要

A power efficient 96.1 dB-SFDR successive approximation register (SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18 μm CMOS. The charge redistribution (CR) design and an extra ΔΣ modulator for capacitance measurement are employed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.