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首页> 外文期刊>Journal of systems architecture >A metaprogrammed C++ framework for hardware/software component integration and communication
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A metaprogrammed C++ framework for hardware/software component integration and communication

机译:用于硬件/软件组件集成和通信的元编程C ++框架

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摘要

With the ever growing complexity of System-on-Chip design, a considerable effort has been made to introduce higher levels of abstraction and to integrate high-level synthesis solutions to the design flow. In such design flows, a uniform communication interface is needed to enable high-level implementations of SoC components regardless of whether they are compiled as software running on a processor or synthesized to dedicated hardware IPs. This paper addresses this issue and proposes a component communication framework that defines an object-oriented remote call mechanism which allows transparent communication across hardware/software boundaries. The proposed framework relies on C++ static metaprogramming techniques to efficiently abstract communication between components implemented using high-level C++. We also define a portability layer that enables the migration of designs throughout different hardware platforms, operating systems, and tools. We assessed the performance and area footprint of our communication infrastructure through the implementation of a voice processing pipeline on top of a Network-on-Chip based architecture. Our results, when compared to previous related works with the same set of capabilities, show that our mechanisms yield small overhead in terms of software memory (up to 64% smaller), FPGA resources (up to 40% smaller), and hardware/software communication latency (up to 51% smaller).
机译:随着片上系统设计的复杂性不断提高,已经做出了相当大的努力来引入更高级别的抽象并将高级综合解决方案集成到设计流程中。在这样的设计流程中,需要统一的通信接口来实现SoC组件的高级实现,而不管它们是编译为在处理器上运行的软件还是合成为专用硬件IP的。本文解决了这个问题,并提出了一种组件通信框架,该框架定义了一种面向对象的远程调用机制,该机制允许跨硬件/软件边界进行透明通信。提出的框架依赖于C ++静态元编程技术来有效地抽象使用高级C ++实现的组件之间的通信。我们还定义了一个可移植层,该层使设计可以在不同的硬件平台,操作系统和工具之间进行迁移。我们通过基于片上网络的体系结构上的语音处理管道的实施,评估了通信基础架构的性能和占地面积。与以前的具有相同功能集的相关作品相比,我们的结果表明,我们的机制在软件内存(小多达64%),FPGA资源(小多达40%)和硬件/软件方面产生了较小的开销。通讯延迟(最多减少51%)。

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