Parametric Yield Modeling Using Hidden Variable Logistic Regression

摘要

Yield modeling is a critical subject in the semiconductor industry and has undergone extensive research. We propose a parametric yield modeling method using a novel technique, namely a hidden variable logistic (HVL) regression. Working with process data, HVL regression can be used to provide an accurate target value and specification limits, which are primary concerns in semiconductor manufacturing, for a particular process variable in a manufacturing step. When defining a success as a status that the semiconductor functions correctly, we can simultaneously estimate the probability of success for the particular process variable and that of success for the process variables other than the particular variable using HVL regression. The proposed parametric yield modeling is used effectively to identify the critical process variables and deal with missing observations. We demonstrate that HVL regression outperforms logistic regression in terms of integrated mean-squared error (IMSE) through Monte Carlo simulation-based investigations.