Scan-Based Structure with Reduced Static and Dynamic Power Consumption

摘要

This paper proposes an efficient technique for reducing the power dissipation in scan-based structures used for testing digital circuits. This method reduces both the switching activity and the static power. It consists of a scan structure along with an algorithm to find the optimum configuration of the structure which results in minimum dynamic and static power consumptions during the scan mode. Since the proposed solution combines the scan cell modification with the complementary algorithm tailored to the new architecture, it is not a pure hardware approach. The technique which can be applied to both full- and partial-scan also may be employed in scan-based BIST architectures. It makes use of multiplexers at the scan cell outputs where adding the multiplexer does not violate the timing requirements of the circuit. During the scan mode, proper outputs are selected by the multiplexers such that they along with the circuit primary inputs suppress the transitions occurred on non-multiplexed scan cells as well as the leakage current during the scan mode. A method for finding these vectors is also proposed. The technique does not affect the fault coverage, the test time, the maximum operating frequency, and the static power consumption of the circuit in the normal mode of operation. It requires no extra control signals and does not have any routing overhead while the area overhead and the required modifications to the traditional scan method are minimal. The effectiveness of this technique is proved by the experiments performed on ISCAS89 benchmark circuits. Compared to traditional scan methods, the results reveal up to a 21% and 80% static and dynamic power reductions, respectively.