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Software Level Power Consumption Models and Power Saving Techniques for Embedded DSP Processors

机译:嵌入式DSP处理器的软件级功耗模型和节能技术

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This paper presents an overview of software level power consumption models and power saving techniques for embedded Digital Signal Processors (DSPs). The paper evaluates their application to the Texas Instruments TMS320VC5510 DSP. Software level power consumption models introduced in the literature are presented, along with their advantages and disadvantages. An enhanced software level power consumption model is proposed for the processor and is shown to achieve an accuracy of 96.8% or greater across a range of benchmarks. Several power saving techniques are presented with discussion of their relevance to the C5510 processor architecture. The significance of various instruction components with respect to consumption are considered in detail.
机译:本文概述了嵌入式数字信号处理器(DSP)的软件级功耗模型和节能技术。本文评估了它们在德州仪器(TI)TMS320VC5510 DSP中的应用。介绍了文献中介绍的软件级功耗模型,以及它们的优缺点。为处理器提出了一种增强的软件级功耗模型,该模型在一系列基准测试中均显示出96.8%或更高的精度。讨论了几种节电技术与C5510处理器体系结构的相关性。详细考虑了各种指令组件相对于消耗的重要性。

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