VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder

摘要

This paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalization technique for logarithmic-maximum-a-posteriori-probability (LOG-MAP) algorithm. We have suggested a decoder architecture based on these techniques for high throughput application. Application-specific-integrated-circuit (ASIC) implementation of the proposed decoder is carried out in 90 nm complementary-metal-oxide-semiconductor (CMOS) process and it has achieved a throughput of 612 Mbps at a maximum clock frequency of 625 MHz with an energy efficiency of 0.1 nJ/bit. Functional verification of the implemented channel decoder is carried out using field-programmable gate-array (FPGA) which is interconnected with logic analyzer via high-speed-data-transfer card. Bit-error-rate (BER) performance of the implemented decoder has shown a coding loss of approximately 0.2 dB in comparison with the simulated BER values.