Area Eifficient Iterative VLSI Array Architecture for Modular Exponentiation

摘要

Security issues will play a crucial role in the majority of future computer and communication systems. The cryptographic algorithms are central to achieve system security. Modular exponentiation is the core arithmetic behind any Public-Key-Cryptosystem (PKC). A novel architecture is proposed to implement modular exponentiation that is scalable with respect to word size and pipeline depth. The entire design is coded in VHDL language. Regularity and local connections makes the algorithm suitable for high performance array implementation in FPGA's. The processing nodes consist of one or two full adders and simple multiplexor. The area and time measures are performed on the optimized design to show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA. We compare our architecture with some previously proposed systolic architecture on the basis of both modular multiplication and exponentiation. The comparison indicates that our architecture offers the higher speed and lower hardware complexity. A fast and area efficient modular exponentiation will considerably enhance the speed and applicability of public key cryptosystem in portable system.