The New Architecture of Chinese Abacus Multiplier

摘要

This study demonstrated a 4×4 bits multiplier that was based on the Chinese abacus. Comparing the simulation results of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, this 4×4 bits abacus multiplier showed a 19.7% and 10.6% delay improvement in 0.35μm and 0.18μm technology respectively than that of the 4×4 bits Braun array multiplier, while power consumption of the 4×4 bits abacus multiplier was 8.7% and 18% lower respectively. The performance: power-consumption*delay of the abacus multiplier is respectively, less about 23.2% and 23.5% also.