Influence of MOSFET parameters in its parasitic capacitances and their impact in digital circuits

摘要

Advanced development of technological processes influenced a wide use of MOSFET transistors in design of integrated digital circuits with high density packages (VLSI). However, in MOSFET transistors parasitic capacitances are present, which will influence on speed of operation in the circuits and dynamic dissipation power. The aim of this paper is to review the influence of channel dimensions, dimensions of source regions, dimensions of drain regions, concentration of impurity (doping concentration) in substrate, concentration of impurity in drain regions (source regions), concentration of impurity sidewalls, level of bias voltage values in particular parasitic capacitances values. Based on the results achieved actions will be determined in order to minimize parasitic capacitance that result in higher speed of operation and lower dynamic power dissipation. Decrease of region dimensions mentioned above depends on technological process capacity for minimal dimensions.