An Asynchronous 32x8-Bit Multiplier Based on LDCVSPG Logic

摘要

An asynchronous high-speed pipelined 32xg-bit array multiplier based on latched differential cascode voltage switch with pass-gate (LDCVSPG) logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation (CSMC's) 0.6 mum CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.