VHDL Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designer's Library

摘要

Floating point arithmetic computation has been widely used today in graphics, digital signal processing, image processing and other applications. Multiplication is the most complex calculation that used in most digital electronic circuit. The multiplier may have large chip area density, high complexity, and is a time consuming computation because the output data size is twice larger than input data size. Complex floating point multiplication required more time to process data and is highly recommended to improve the computation speed. The performance in terms of computation and processing speed is one of the major factors in today's Very/Ultra Large Scale Integration (VLSI/ULSI) system design. The objective of this research is to design a 32-bit floating point multiplier for Very high speed integrated circuit Hardware Description Language (VHDL) designer's library that consists of mantissas multiplier, normalizer, exponent adder, and signer for VHDL designer's library that lack of floating point multiplier module. Booth radix-4 algorithm is used in the multiplier, mainly due to the simplicity of this algorithm to be modeled using VHDL and at the same time it provides good performance. The 32-bit floating point multiplier is tested on Arria II GX chip to determine their performance in terms of slack, maximum frequency and minimum clock period by using TimeQuest Timing Analyzer. Booth radix-4 multiplier in Arria II GX (EP2AGX45CU17I3) produces a maximum frequency of 206.14 MHz and minimum allowed clock period of 5 ns. Benchmarking has been carried out between the Booth radix-4 and Wallace Tree multipliers, since Wallace Tree multiplier can provide better performance to the VLSI system design. The resource consumption of Booth radix-4 multiplier is 88.8% less than the Wallace Tree multiplier and the performance of Booth radix-4 multiplier is almost equal to the Wallace Tree multiplier.