Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs

摘要

In this paper, we model a high speed Arithmetic synthesizable modified Fused Multiply Add Unit (FMA) capable of implementing the following operations: Addition/subtraction, Multiplication. With area-speed tradeoff limitation, our focus is on modeling high speed Arithmetic units with moderate area increase. Thus, we focus on developing units that share the same hardware. We have modeled a high speed arithmetic Modified fused multiply add unit (A*B + C ) Capable of addition/subtraction and multiplication. We have concentrated on reducing the delay in critical path by identifying the most time consuming operations in the critical path of a basic multiply Add fused unit. CAD tools have been implemented to model our system. Once modeled and synthesized, the system is downloaded onto a FPGAs chip. The synthesized chip is a stand alone FMA unit capable of implementing the operations mentioned. Synthesis tools have been implemented to evaluate our designs. Our results show that the estimated minimum delay of our designed unit is 4. 624ns.