Strain measurement in micro-electronic packages using the digital image correlation method

摘要

Due to the reduced size and increased density of electronic devices, there has been increasing use of high-density surface mounting technology such as flip-chip (FC) assemblies and multilayer board interposers. FC assemblies, unlike the previous quad fiat packages, are not connected by leads but have surfaces connected by solder bumps and, therefore, are susceptible to thermal stress due to the coefficient of thermal expansion (CTE) mismatches between the chips and interposers. A resin seal/encapsu-lant, using underfill (UF), is used to mitigate this thermal stress, but it is known that, depending on the characteristics of this, the thermal fatigue strength reliability may vary. In multilayer boards, the toughness and CTE of a printed circuit board when finished may change depending on the thickness and characteristics of the buildup (BU) and may have a significant effect on the bending behaviour of the package and connection reliability of the solder bumps.