A reverse engineering approach to generate a virtual plant model for PLC simulation

摘要

A reverse engineering approach to generate a virtual plant model is proposed. The model can be used for programmable logical controller (PLC) simulation. The virtual plant model for the PLC simulation consists of virtual device models and must interact with the input and output signals of a PLC. The behavior of a virtual device model should be the same as that of real device. Conventionally, the discrete event system specifications (DEVS) formalism has been used to represent the behavior of a virtual device model. Modeling using DEVS formalism, however, requires in-depth knowledge of the simulation area, as well as a significant amount of time and effort. One of the key ideas of the proposed methodology is to provide a method to generate a virtual plant model using both log data (time-stamped signal history) and a PLC I/O signal table extracted from the existing production system. The proposed reverse engineering approach provides two major benefits: (1) significant reduction in the time and effort for the construction of a reliable virtual plant model of a current production system, which can be referenced for newly planned production systems, and (2) reduction in the stabilization time of a production system through PLC simulation. The proposed approach was implemented and applied to an automated production line.