Simulation of Losses in Thin-Film Silicon Modules for Different Configurations and Front Contacts

摘要

A simulation tool for the quantification of electrical losses in thin-film modules using a one- and two-dimensional electrical PSpice model is presented. Two main sources of electrical losses are examined: monolithic contacts (MC) and front contacts made of a transparent conductive oxide (TCO) layer with or without a metal finger grid. Our study was focussed on amorphous and micromorph silicon modules in substrate or superstrate configuration. Results show that front contact losses (TCO losses and finger losses) prevail. While, under assumption that their subcell performances are the same, performance of amorphous silicon (a-Si) modules do not depend on the configuration, the superstrate micromorph silicon module has a relatively slight (below 2 percent) advantage over the substrate counterpart due to lower electrical losses in the MC. Losses of the front contact made of a thick TCO layer Sr of thin TCO layer and metal finger grid on top were studied for both modules in substrate configuration and optimisation results are presented. Use of thin TCO layer and optimised finger grid and solar cell geometry is competitive and these modules can even outperform the optimised amorphous or micromorph silicon module with thick TCO front contact. In all optimised cases under standard test conditions, total relative losses can be minimised to around 10 percent.