An evaluation of asynchronous addition

摘要

There is considerable interest at present in the design ofnasynchronous systems based on the use of self-timing components fornarithmetic and other operations. Amongst the advantages claimed fornasynchronous design are ease of design, high speed, low power, andndevice speed independence. An often quoted example of the speednimprovement possible from self-timed hardware is parallel binarynaddition, where the carry signals in the worst case must propagatenthrough n stages before the sum can be guaranteed correct. In practice,nhowever, it is not possible to achieve significant speed advantage fromnthe method, and this paper shows that asynchronous adders only give anperformance improvement over more conventional hardware in very limitednconditions, where the size and regularity of the layout are at a premium