ILP-based cost-optimal DSP synthesis with module selection and dataformat conversion

摘要

In high-level synthesis, a data flow graph (DFG) description of annalgorithm is mapped onto a register transfer level description of annarchitecture. Each node of the DFG is scheduled to a specific time andnallocated to a processor. In this paper, we present new integer linearnprogramming (ILP) models which generate a blocked schedule for a DFGnwith automatic retiming, pipelining, and unfolding while performingnmodule selection and dataformat conversion. A blocked schedule is anschedule which overlaps multiple iterations of the DFG to guarantee anprocessor optimal schedule. During module selection an appropriatenprocessor is chosen from a library of processors to construct a costnoptimal architecture. Furthermore, we also include the cost and latencynof data format conversions between processors of differentnimplementation styles. We also present a new formulation for minimizingnthe unfolding factor of the blocked schedule. The approach presented innthis paper is the only systematic approach proposed so far to includenimplicit unfolding and to perform synthesis using nonuniform processornstyles and data format converters