Quantitative study of the impact of design and synthesis options onprocessor core performance

摘要

In this paper, we present experimental results obtained during thenmodeling, design, and implementation of a full set of versions of SPARCnv.8 Integer Unit cores aimed at embedded applications. VHDL is thendescription language, Synopsys is the tool used for logical synthesis,nand Duet Technologies' Epoch for obtaining the physical layout of thenfinal circuits. These are mapped to 0.50- and 0.35-Μm, three metalnlayer processes in order to study the impact of VLSI scaling on SPARCnmicroarchitectural features. The quantitative results obtainedncharacterize suitable points in the design space. They show the extentnto which microarchitecture, design, datapath granularity, and megacellndecisions affect performance and cost functions. Design spacenexploration down to physical layouts is made possible by modelingntechniques based on configurable VHDL descriptions