True single-phase adiabatic circuitry

摘要

Dynamic logic families that rely on energy recovery to achieve lownenergy dissipation control the flow of data through gate cascades usingnmultiphase clocks. Consequently, they typically use multiple clockngenerators and can exhibit increased energy consumption on their clockndistribution networks. Moreover, they are not attractive for high-speedndesign due to their high complexity and clock skew management problems.nIn this paper, we present TSEL, the first energy-recovering (a.k.a.nadiabatic) logic family that operates with a single-phase sinusoidalnclocking scheme. We also present SCAL, a source-coupled variant of TSELnwith improved supply voltage scalability and energy efficiency. Optimalnperformance under any operating conditions is achieved in SCAL using antunable current source in each gate. TSEL and SCAL outperform previousnadiabatic logic families in terms of energy efficiency and operatingnspeed. In layout-based simulations with 0.5 Μm standard CMOS processnparameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCALnfunction correctly for operating frequencies exceeding 200 MHz. Inncomparison with corresponding CLAs in alternative logic styles thatnoperate at minimum supply voltages, CLAs designed in our single-phasenadiabatic logic families are more energy efficient across a broad rangenof operating frequencies. Specifically, for clock rates ranging from 10nto 200 MHz, our andbit SCAL CLAs are 1.5 to 2.5 times more energynefficient than corresponding adders developed in PAL and 2N2P and 2.0 ton5.0 times less dissipative than their purely combinational or pipelinednCMOS counterparts