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Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm

机译:面向VLSI的FELICS算法的高通量无损图像压缩引擎的设计与分析

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摘要

In this paper, the VLSI-oriented fast, efficient, lossless image compression system (FELICS) algorithm, which consists of simplified adjusted binary code and Golomb-Rice code with storage-less k parameter selection, is proposed to provide the lossless compression method for high-throughput applications. The simplified adjusted binary code reduces the number of arithmetic operation and improves processing speed. According to theoretical analysis, the storage-less k parameter selection applies a fixed k value in Golomb-Rice code to remove data dependency and extra storage for cumulation table. Besides, the color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Based on VLSI-oriented FELICS algorithm, the proposed hardware architecture features compactly regular data flow, and two-level parallelism with four-stage pipelining is adopted as the framework of the proposed architecture. The chip is fabricated in TSMC 0.13-¿m 1P8M CMOS technology with Artisan cell library. Experiment results reveal that the proposed architecture presents superior performance in parallelism-efficiency and power-efficiency compared with other existing works, which characterize high-speed lossless compression. The maximum throughput can achieve 4.36 Gb/s. Regarding high definition (HD) display applications, our encoding capability can achieve a high-quality specification of full-HD 1080p at 60 Hz with complete red, green, blue color components. Furthermore, with the configuration as the multilevel parallelism, the proposed architecture can be applied to the advanced HD display specifications, which demand huge requirement of throughput.
机译:本文提出了一种面向VLSI的快速,高效,无损图像压缩系统(FELICS)算法,该算法由简化的调整后的二进制代码和具有无存储k参数选择的Golomb-Rice代码组成,旨在为无损压缩提供方法。高通量应用。简化的调整后的二进制代码减少了算术运算的数量并提高了处理速度。根据理论分析,无存储的k参数选择在Golomb-Rice代码中应用了固定的k值,以消除数据依赖性并为累加表增加存储空间。此外,还提出了色差预处理,以通过简单的算术运算来提高编码效率。基于面向VLSI的FELICS算法,该硬件体系结构具有紧凑的规则数据流,并采用具有四级流水线的两级并行性作为该体系结构的框架。该芯片采用台积电0.13-μm1P8M CMOS技术和Artisan单元库制造。实验结果表明,与现有的其他工作相比,所提出的体系结构在并行效率和功率效率方面均表现出优异的性能,这是高速无损压缩的特征。最大吞吐量可以达到4.36 Gb / s。对于高清(HD)显示应用,我们的编码能力可以达到60 Hz的全高清1080p的高质量规格,并具有完整的红色,绿色,蓝色分量。此外,通过配置为多级并行,所提出的体系结构可以应用于高级高清显示规范,这对吞吐量有巨大的要求。

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