ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling

摘要

Loopback testing is a powerful technique for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) pair embedded in a mixed-signal system-on-chip (SoC). While attractive, its performance is generally limited by the achievable test resolution and the potential fault masking problem. In this work, a loopback linearity testing technique for an ADC/DAC pair is presented; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the required test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.