Multi-Threshold Voltage FinFET Sequential Circuits

摘要

New multi threshold voltage (multi-${V}_{rm th}$) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the average leakage power of the multi-${V}_{rm th}$ sequential circuits are reduced by up to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits in a single threshold voltage (single-${V}_{rm th}$) tied-32 nm-gate FinFET technology. Furthermore, the area is reduced by up to 21% with the new sequential circuits as compared to the circuits with single-${V}_{rm th}$ tied-gate FinFETs.