A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique

摘要

This paper presents a linearity-enhanced 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a high-speed and low-noise comparator. A p-well floating technique for linearity improvement of sampling switch is prop