Resistive interpolation biasing: a technique for compensating linear variation in an array of MOS current sources

摘要

A new technique called resistive interpolation biasing for accurately biasing a large number of analog cells on a VLSI chip is presented. Variations in oxide thickness, mobility, doping concentration, etc., cause inaccuracies in current ratios of two identically biased transistors if they are placed sufficiently far apart on a chip. The proposed technique compensates for these inaccuracies without using any sampling or switching. The technique has been verified using a 2 /spl mu/m n-well CMOS process. Measurements show a factor of 3 improvement in terms of current ratio accuracy when the resistive interpolation technique is used. The circuit can be implemented with a small chip area and low power dissipation. This technique finds applications where extensive current duplication over a large area is required (e.g., analog memories, D/A converters, continuous-time filters, imaging arrays, neural networks, and fuzzy logic systems).