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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A monolithic digital clock-generator for on-chip clocking of custom DSP's
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A monolithic digital clock-generator for on-chip clocking of custom DSP's

机译:单片数字时钟发生器,用于定制DSP的片内时钟

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This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 /spl mu/m standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage.
机译:本文展示了用于定制设计的强大且易于实现的时钟发生器。它是全数字设计,适用于高速时钟和低压应用。这种时钟方法是数字的,并且避免了诸如锁相环或延迟线环路之类的模拟方法。取而代之的是,时钟发生器基于环形计数器,该计数器在正确的周期数后停止环形振荡器。本文描述了使用片上时钟策略的385 MHz时钟和15 MHz定制DSP应用。原型以0.8 / spl mu / m的标准CMOS工艺制造。这种时钟方法的主要优点是坚固,体积小,功耗低,并且可以在非常低的电源电压下工作。

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