Bufferless broadcasting: a low power distributed circuit technique for broadcasting 10-Gb/s chip input signals

摘要

Bufferless distributed circuit (BDC) broadcasting is proposed as a technique for broadcasting high-speed chip input signals to a series of on-chip destination cells as needed in crosspoint switch, parallel multiplier, distributed amplifier, etc., chip designs. In contrast with conventional techniques that use an on-chip buffer to assist broadcasting, BDC broadcasting offers the advantage of lower signal delay and power dissipation. In an experimental GaAs heterojunction bipolar transistor (HBT) 8/spl times/4 crosspoint switch assembly, BDC broadcasting was found to achieve a 40% power savings with little or no penalty in jitter or bit error rate performance at a 10-Gb/s data rate.