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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter
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A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter

机译:一个1.5 V,4.1 mW双通道音频delta-sigma D / A转换器

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The paper describes a stereo digital-to-analog converter intended for portable digital-audio which operates at 1.5 V and consumes only 4.1 mW. A 15-level quantization, third-order delta-sigma was employed to reduce digital operation speed, relax out-of-band filtering requirements, and enhance immunity to clock jitter. The use of direct charge transfer switched-capacitor technique in the multibit reconstruction DAC reduces kT/C noise and element mismatch without increase of power dissipation. The data weighted averaging algorithm suppresses nonlinearity caused by capacitor mismatch by first-order noise-shaping, thereby making mismatch-induced noise negligible. The stereo audio DAC achieves 90 dB dynamic range and 81 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The 5.3 mm/sup 2/ chip is fabricated in a 0.6 /spl mu/m CMOS technology which includes low-threshold devices.
机译:本文介绍了一种用于便携式数字音频的立体声数模转换器,其工​​作电压为1.5 V,功耗仅为4.1 mW。采用15级量化三阶delta-sigma来降低数字运算速度,放宽带外滤波要求并增强对时钟抖动的抵抗力。在多位重构DAC中使用直接电荷转移开关电容器技术可在不增加功耗的情况下降低kT / C噪声和元件失配。数据加权平均算法通过一阶噪声整形来抑制由电容器失配引起的非线性,从而使失配引起的噪声可以忽略不计。立体声音频DAC在20 kHz通带上可实现90 dB的动态范围和81 dB的峰值信噪加失真比。 5.3 mm / sup 2 /芯片采用0.6 / spl mu / m CMOS技术制造,该技术包括低阈值器件。

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