A 1 Gbit synchronous dynamic random access memory with anindependent subarray-controlled scheme and a hierarchical decodingscheme

摘要

A prototype 1 Gbit synchronous DRAM with independentnsubarray-controlled isolation and hierarchical decoding schemes isndemonstrated to alleviate the difficulties encountered in high-densityndevices with regard to failure analysis and performance optimization.nThe scheme to isolate memory arrays from “hard” defects andnto overcome the dc leakages of “soft” defects with externalnsources allows monitoring of the leakage current for the defect analysisnand testing of the device without being limited by the capabilities ofnon-chip voltage sources. A hierarchical decoding scheme with a dynamicnCMOS series logic predecoder achieves improvements in circuit speed,npower, and complexity. As a result, evaluation of the prototype devicesncan be facilitated, and the optimized circuit schemes achieve enhancedncircuit performance. A fully working 1 Gbit synchronous DRAM with a chipnsize of 570 mm2 was fabricated using a 0.16 Μm CMOSnprocess and tested for excellent functionality up to 143 MHz