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A mixed-signal array processor with early vision applications

机译:具有早期视觉应用的混合信号阵列处理器

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Many early vision tasks require only 6 to 8 b of precision. Fornthese applications, a special-purpose analog circuit is often a smaller,nfaster, and lower power solution than a general-purpose digitalnprocessor, but the analog chips lack the programmability of digitalnimage processors. This paper presents a programmable mixed-signal arraynprocessor which combines the programmability of a digital processor withnthe small area and low power of an analog circuit. Each processor cellnin the array utilizes a digitally programmable analog arithmetic unitnwith an accuracy of 1.3%. The analog arithmetic unit utilizes a uniquencircuit that combines a cyclic switched-capacitor analog-to-digitalnconverter (ADC) and digital-to-analog converter (DAC) to performnaddition, subtraction, multiplication, and division, Each processorncell, fabricated in a 0.8-Μm triple-metal CMOS process, operates at anspeed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 Μmnby 270 Μm of silicon area. An array of these processor cellsnperformed an edge detection algorithm and a subpixel resolutionnalgorithm
机译:许多早期的视觉任务只需要6至8 b的精度。对于这些应用,专用模拟电路通常比通用数字处理器具有更小,更快,功耗更低的解决方案,但是模拟芯片缺乏数字图像处理器的可编程性。本文提出了一种可编程混合信号阵列处理器,它将数字处理器的可编程性与模拟电路的小面积和低功耗结合在一起。阵列中的每个处理器单元都使用精度为1.3%的数字可编程模拟算术单元。模拟算术单元利用独特的电路,该电路结合了循环开关电容器模数转换器(ADC)和数模转换器(DAC)来执行加,减,乘和除运算,每个处理器单元以0.8-微米三重金属CMOS工艺,以0.8 MIPS的速度运行,在5 V时消耗1.8 mW的功率,并使用700微米×270微米的硅面积。这些处理器单元的阵列执行边缘检测算法和亚像素分辨率算法

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