CMOS high-frequency switched-capacitor filters fortelecommunication applications

摘要

A digitally programmable high-frequency switched-capacitor filternfor use in a switched digital video (SDV/VDSL) link is described. Thenhighest available clock frequency in the system is 51.84 MHz (fsn=2fclock=103.68 MHz for double sampling) while thenthree desired low-pass corner frequencies (fc) are 8,12, andn20 MHz. The double-sampling, bilinear, elliptic, fifth-ordernswitched-capacitor filter meets the desired -40-dB attenuation at 1.3 fnc, and -30 dB at 1.25 fc. For the 12-MHz cornernfrequency setting, given the 2Vpp differential input, thenmeasured worst case total harmonic distortion is -60 dB, withnsignal-to-noise ratio of 54 dB. The analog power dissipation is 125 mWnfrom a 5-V power supply. The test results indicate that the clocknfrequency can be increased to 73 MHz without any ill effects. Morenmeasurements verify that an all-digital CMOS implementation, utilizingnmetal-sandwich capacitors, performs as well as the special-layer analogncapacitors implementation, with a small reduction in the absolute cornernfrequencies. The prototype IC's are fabricated in a 0.35-Μm 5-V (0.48nΜm drawn) CMOS process