A 1.0-V VDD CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-Μm CMOS process

摘要

In this paper, an architecture to design a CMOS active-pixel sensor (APS) in an extremely low-voltage environment imposed by advanced CMOS technology is proposed. A complementary active pixel sensor (CAPS) architecture is developed to allow a CMOS active pixel to operate at a voltage below 1 V VDD without using bootstrapping techniques. A fixed voltage deference (FVD) method with correlated double sampling is used to increase the dynamic range of the readout circuit. Both the CAPS and FVD readout circuits together, with an 8-b analog-to-digital converter, are implemented in a commercially available 0.25-Μm, single-poly and five-metal CMOS process. Measurement results show that the circuit is functional at a VDD below 1 V with 15-dB added dynamic range compared with a conventional CMOS APS architecture.