On-chip ramp generators for mixed-signal BIST and ADC self-test

摘要

A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of /spl plusmn/175/spl mu/V. Experimental and theoretical results are in good agreement.