首页> 外文期刊>IEEE Journal of Solid-State Circuits >An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing
【24h】

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

机译:具有用于模拟测试的数字接口的集成频率响应表征系统

获取原文
获取原文并翻译 | 示例
       

摘要

Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-mum technology employs only 0.3mm2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip
机译:当前和将来的集成系统都需要经济高效的测试解决方案。为了满足这种需求,这项工作提出了一个非常紧凑的混合信号测试系统。它在模拟电路的多个节点上对整个频率范围内的幅度和相位响应进行表征。该系统的控制输入和输出是数字的,从而可以通过低成本的数字自动测试设备对片上系统(SoC)或系统级封装(SiP)中的模拟组件进行测试。提出了用于测试系统实施的稳健且面积高效的构建块,包括用于精确幅度和相位检测的线性化模拟乘法器,宽调谐范围的压控振荡器和低功耗算法模数转换器。介绍了他们的个人设计注意事项和性能结果。台积电CMOS 0.35毫米技术的完整原型仅占用0.3mm2的面积。通过在集成在同一芯片中的两个不同的四阶连续时间滤波器的各个节点上执行高达130 MHz的频率响应特性来演示该测试系统的操作

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号