A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process

摘要

This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- $mu$m CMOS process, the receiver measures maximum S11 of ${-}$ 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than ${-}$13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 $^{circ}$, respectively. The transmitter achieves a minimum output P–1 dB of ${-}$8.2 dBm, sideband rejection of better than ${-}$42.2 dBc, and LO leakage of smaller than ${-}$ 46.5 dBc.