An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

摘要

A multiple-level 2-bit/cell storage technique for DRAMs (dynamic random-access memories) has been developed. The total RAM area is reduced and the cell array is cut in half. Since the memory cell area is especially defect-sensitive, this technique is highly effective for process yield improvement. Reasonable access time has been realized with this technique: 170 ns is still fast enough for many ASIC (application-specific integrated circuit) memory applications. This technique meets the requirement of high density and moderate speed. It was found that the 2-bit/cell storage technique is suitable for macrocell or memory-on-logic type application.