Row and column sensitive faults in RAMs are a class of faults in which the contents of a cell become sensitive to the contents of the row and column containing the cell in presence of a fault. A fault model that includes such faults is formally defined, and an algorithm to detect faults on the basis of this model is presented. Two different implementations of the algorithm for a VLSI built-in-self-test (BIST) environment are presented. They are a random-logic-based design and a microcode-based design. Additional properties of the algorithm, such as its capability to detect stuck-at faults, coupling faults, and conventional pattern sensitive faults, are identified.
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