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A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization

机译:具有数字锁相环同步功能的90–240 MHz磁滞控制DC-DC Buck转换器

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This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation outside undesirable power supply resonance bands. The stability and loop dynamics of the proposed converter is analyzed using an analog equivalent PLL behavioral model which describes the dc-dc converter as a voltage-controlled oscillator (VCO). We demonstrate a 90–240 MHz single phase converter with fast hysteretic control and output conversion range of 33%–80%. The converter achieves an efficiency of 80% at 180 MHz, a load response of 40 ns for a 120 mA current step and a peak-to-peak ripple less than 25 mV. The circuit was implemented in 130 nm digital CMOS process.
机译:本文报告了一种基于数字锁相环(D-PLL)的频率锁定技术,用于高频滞回控制的DC-DC降压转换器。拟议的转换器可在较宽的输出电压范围内实现恒定的工作频率,从而消除了开关频率对占空比或电压转换范围的依赖。 D-PLL可以在很宽的参数范围内进行编程,并且可以与时钟基准同步,以确保在不希望的电源谐振频带之外进行适当的频率锁定和开关操作。使用模拟等效PLL行为模型分析了拟议转换器的稳定性和环路动力学,该模型将dc-dc转换器描述为压控振荡器(VCO)。我们演示了一种90–240 MHz单相转换器,具有快速的磁滞控制和33%–80%的输出转换范围。该转换器在180 MHz时达到80%的效率,对于120 mA的电流阶跃,负载响应为40 ns,峰峰值纹波小于25 mV。该电路采用130 nm数字CMOS工艺实现。

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