首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error

机译:具有±1.5%频率和±3.6%均流误差的6A,93%峰值效率,四相数字同步磁滞降压转换器

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摘要

A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc-dc converter achieves 93% peak efficiency for Vi = 2 V and Vo = 1.6 V.
机译:提出了一种具有数字频率同步,在线比较器失调校准和数字均流控制的四相准电流模式迟滞降压转换器。迟滞转换器的开关频率与输入时钟参考数字同步,在3-9.5 MHz的开关频率范围内误差小于±1.5%。在线失调校准消除了磁滞比较器的输入参考失调,并实现了±1.1%的电压调节精度。通过占空比校准的基于延迟线的脉宽调制发生器,可实现±3.6%的最大均流误差,而不会影响相位同步时序。在轻载条件下,可以禁用各个转换器的相,并且将末级功率转换器的输出级分段以提高效率。当V i = 2 V和V o = 1.6 V时,dc-dc转换器的峰值效率达到93%。

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