Rapid yield estimation as a computer aid for analog circuit design

摘要

A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulations, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage operational amplifiers and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield is presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer.