首页> 外文期刊>Software >Application of Deadlock Risk Evaluation of Architectural Models
【24h】

Application of Deadlock Risk Evaluation of Architectural Models

机译:死锁风险评估在建筑模型中的应用

获取原文
获取原文并翻译 | 示例
       

摘要

Software architectural evaluation is a key discipline used to identify, at early stages of a real-time system (RTS) development, the problems that may arise during its operation. Typical mechanisms supporting concurrency, such as semaphores, mutexes or monitors, usually lead to concurrency problems in execution time that are difficult to be identified, reproduced and solved. For this reason, it is crucial to understand the root causes of these problems and to provide support to identify and mitigate them at early stages of the system lifecycle. This paper aims to present the results of a research work oriented to the development of the tool called 'Deadlock Risk Evaluation of Architectural Models' (DREAM) to assess deadlock risk in architectural models of an RTS. A particular architectural style, Pipelines of Processes in Object-Oriented Architectures-UML (PPOOA) was used to represent platform-independent models of an RTS architecture supported by the PPOOA -Visio tool. We validated the technique presented here by using several case studies related to RTS development and comparing our results with those from other deadlock detection approaches, supported by different tools. Here we present two of these case studies, one related to avionics and the other to planetary exploration robotics.
机译:软件体系结构评估是用于在实时系统(RTS)开发的早期阶段确定其运行过程中可能出现的问题的关键学科。支持并发的典型机制,例如信号量,互斥量或监视器,通常会导致执行时间上的并发问题,这些问题很难被识别,再现和解决。因此,至关重要的是要了解这些问题的根本原因,并提供支持以在系统生命周期的早期阶段识别和缓解这些问题。本文旨在介绍针对开发称为“建筑模型的死锁风险评估”(DREAM)的工具的研究工作的结果,以评估RTS的建筑模型中的死锁风险。一种特殊的体系结构样式,即面向对象体系结构中的流程管道(UML)(PPOOA)用于表示由PPOOA -Visio工具支持的RTS体系结构的平台独立模型。我们通过使用与RTS开发相关的几个案例研究,并将我们的结果与其他死锁检测方法(在不同工具的支持下)的结果进行比较,验证了此处介绍的技术。在这里,我们介绍了其中两个案例研究,一个与航空电子相关,另一个与行星探测机器人相关。

著录项

  • 来源
    《Software》 |2012年第9期|p.1137-1163|共27页
  • 作者单位

    Airbus Military, John Lennon Av., Getafe 28906, Spain;

    Industrial Engineering School, Technical University of Madrid (UPM), Jose Gutierrez Abascal 2,Madrid 28006, Spain;

    Telecommunications Engineering School, Technical University of Madrid (UPM), Avenida Complutense 30,Madrid 28040, Spain;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    deadlock; software architecture; MBSE; UML; concurrency;

    机译:僵局;软件架构;MBSE;UML;并发;
  • 入库时间 2022-08-17 13:03:49

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号