80-100 V low-side lateral double-diffused metal oxide semiconductor device with sided isolation of 0.35 µm complementary metal oxide semiconductor-compatible process

摘要

In this study, a novel 80-100 V multiple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor (LDMOS) transistor with shallow trench isolation (STI) on both sides of the structure is developed and simulated using a Sentaurus process simulator. The proposed multiple RESURF LDMOS structure achieves benchmark specific on-state resistance while maintaining breakdown voltages of 80 and 100 V with better safe-operating area (SOA) performance. The key feature of this novel n-channel LDMOS (NLDMOS) device is the presence of linear p-top rings in the n-drift region. The optimization of the linear p-top mask design and concentration of p-top in the region is performed in order to achieve benchmark on-state resistance with the desired breakdown voltage. Linear p-top helps the diffusion current to move faster in the drift region, which helps to reduce on-state resistance.