The Impact Of Wafer Nanotopography On Threshold Voltage Variation In Nand Flash Memory Cells Fabricated With Poly-silicon Chemical Mechanical Polishing

摘要

Based on simulation, the threshold voltage (V_T) variation for NAND flash memory cells fabricated with the self-alignment of the poly-silicon floating gate is expected to be related to the peak-to-valley value (PV) of wafer nanotopography. After chemical and mechanical polishing (CMP) of the poly-silicon floating gate, the PV of the remaining height of the poly-silicon floating gate linearly increased with the PV of wafer nanotopography. As a result, the V_T variation linearly increased with the PV of the remaining height of the poly-silicon floating gate after CMP. These simulation results show, in particular, that the V_T variation of NAND flash memory cells induced by wafer nanotopography becomes larger and larger as the device size becomes smaller and smaller.