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Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

机译:栅电极功函数设计的凹陷沟道纳米级MOSFET的二维阈值电压模型和设计考虑因素:I

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摘要

This paper discusses a threshold voltage model for novel device structure: gate electrode work function engineered recessed channel (GEWE-RC) nanoscale MOSFET, which combines the advantages of both RC and GEWE structures. In part I, the model accurately predicts (a) surface potential, (b) threshold voltage and (c) sub-threshold slope for single material gate recessed channel (SMG-RC) and GEWE-RC structures. Part II focuses on the development of compact analytical drain current model taking into account the transition regimes from sub-threshold to saturation. Furthermore, the drain conductance evaluation has also been obtained, reflecting relevance of the proposed device for analogue design. The analysis takes into account the effect of gate length and groove depth in order to develop a compact model suitable for device design. The analytical results predicted by the model confirm well with the simulated results. Results in part I also provide valuable design insights in the performance of nanoscale GEWE-RCrn MOSFET with optimum threshold voltage and negative junction depth (NJD), and hence serves as a tool to optimize important device and technological parameters for 40 nm technology.
机译:本文讨论了一种新颖的器件结构的阈值电压模型:栅电极功函数工程凹陷沟道(GEWE-RC)纳米级MOSFET,它结合了RC和GEWE结构的优点。在第I部分中,该模型准确地预测了(a)表面电位,(b)阈值电压和(c)亚材料栅极凹槽(SMG-RC)和GEWE-RC结构的亚阈值斜率。第二部分着眼于紧凑型分析漏电流模型的开发,其中考虑了从亚阈值到饱和的过渡机制。此外,还获得了漏极电导率评估,反映了拟议的模拟设计设备的相关性。该分析考虑了浇口长度和凹槽深度的影响,以便开发出适用于器件设计的紧凑模型。模型预测的分析结果与模拟结果吻合良好。第一部分的结果也为具有最佳阈值电压和负结深度(NJD)的纳米级GEWE-RCrn MOSFET的性能提供了有价值的设计见解,因此,它可作为优化40 nm技术重要器件和技术参数的工具。

著录项

  • 来源
    《Semiconductor science and technology》 |2009年第6期|104-113|共10页
  • 作者单位

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi,South Campus, Benito Juarez road, Dhaula Kuan, New Delhi, India;

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi,South Campus, Benito Juarez road, Dhaula Kuan, New Delhi, India;

    Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, Karampura,New Delhi, India;

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi,South Campus, Benito Juarez road, Dhaula Kuan, New Delhi, India;

    Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi,South Campus, Benito Juarez road, Dhaula Kuan, New Delhi, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
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  • 入库时间 2022-08-18 01:31:57

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