New Bonding Process Offers 'Penalty-Free' 3-D Integration

摘要

We're going to do for the semiconductor industry what steel did for the building industry," says Doug Mil-ner, CEO of a new company called Ziptronix (Research Triangle Park, N.C.), a spin-out of the Research Triangle Institute (RTI). This is no idle boast: He's talking about a bonding process that was under development at RTI for the past eight years and that Ziptronix ― the first spin-out of RTI ― is now in charge of commercializing. The "zip" in Ziptronix stands for zero integration penalty, and that's what Milner claims is possible with the company's material bonding process, which works at room temperature, employs standard fab process equipment and results in a very strong covalent bond. He expects it to enable the fabrication of 3-D devices without the compromises or costs associated with system-on-a-chip (SoC) or sys-tem-in-a-package (Figure). The company also sees benefits in fabricating MEMS and rf devices, as well as more exotic applications like indium phosphide on CMOS. "We have proof of concept projects in each one of those areas that are active now," Milner said. "We anticipate that we'll be in production in the engineered substrate space by the end of this year."