Acoustic Screening: Uncovers Package Defects

摘要

In the past decade or so, the minimum size of solder bumps used in flip-chips has shrunk drastically, as has the offset between the chip face and the substrate. At the same time, the number of solder bump interconnects that may be attached to a single die has increased greatly. This ongoing miniaturization has made possible greater product complexity and increased functionality, but it also means that the packaging anomalies that can break the interconnects have become smaller. If voids and other packaging anomalies always caused detectable circuitry damage more or less instantaneously ― as soon as they formed, or at least before in-circuit test or functional testing ― then high reliability would be far easier to achieve. The problem is that the action of these anomalies is very unpredictable. A void typically forms when the flowing underfill material traps an air bubble. If the void lodges next to a solder bump, there is a good possibility that the solder will eventually creep into the void, leading to the collapse of the bump and the breaking of the interconnect.