Reliability Fundamentals at 45 nm

摘要

Scaling to 45 nm and beyond has the unfortunate effect of pushing CMOS materials closer to their intrinsic reliability limits. At the 65 nm node, gate oxide thickness is ～1.2 nm, with a leakage of ～100 A/cm~2 at 1.0 V. Scaling further, issues of high current densities, voltage overshoots, localized hot spots on the chip and high thermal resistance packaging become concerns, as explained by a recent presentation by Joe McPherson, senior fellow of Texas Instruments (Dallas) at the Design Automation Conference in San Francisco. McPherson addressed the impact of scaling on gate leakage, negative bias temperature instability (NBTI), RC delay, electromigration, stress migration and Joule heating. Though in most cases there is a trend toward degraded reliability with continued scaling, the industry is finding remedies so that device reliability specifications can be met.