Cleaning's Role in High-k/Metal Gate Success

摘要

The International Technology Roadmap for Semiconductors (ITRS) projects that future high-performance processes will require transistor gate stacks to have an equivalent oxide thickness (EOT) of <1.0 nm for the 45 nm node. As EOTs scale to < 2 nm, the polysilicon gate depletion becomes a significant problem, and metal electrodes, whose depletion regions are almost nonexistent, become necessary. Importantly, when the EOT is scaled this drastically, the bottom interface quality has a significant impact on device performance. Additionally, the integration of high-k and two metals for the nMOS and pMOS transistors into the process flow is very complex. This article reviews the state-of-the-art of surface preparation before high-k deposition and of metal wet etch as part of the CMOS dual metal gate fabrication process.