3-D ICs Are Cost-Driven, Evolutionary

摘要

Despite the somewhat revolutionary nature of 3-D integration at the device level, the technology is really evolutionary according to the panelists on Semiconductor International's latest webcast, "Through-Silicon Vias: Ready for Prime Time?" Phil Garrou, IEEE Fellow and consultant with Microelectronic Consultants of North Carolina (Research Triangle Park, N.C.). mapped out the evolutionary way in which the three components of 3-D ICs, through-silicon vias (TSVs), wafer thinning and wafer bonding, are being implemented. "In image sensors for digital cameras, TSVs are used without chip stacking. In the next generation, the sensors will be stacked with DSPs. Sony is stacking memory on logic in the 90 nm PS3 chip. Infineon and IBM are implementing face-to-face bonding in their SOLID technology. Samsung and others are using TSVs in memory stacking, but the vias go through the existing bond pads, so chip redesign has yet to take place to fully optimize the 3-D implementation."