A Unified Drain-Current Model of Silicon Nanowire Field-Effect Transistor (SiNWFET) for Performance Metric Evaluation

摘要

The critical dimensions of silicon-based devices have reached below 100 nm length scale. In order to overcome short channel effects due to downscaling, research and development of new structures and materials is crucial. With improved gate control, silicon nanowire (SiNW) is a promising candidate in scaled-down field-effect transistors (FETs) that can replace the conventional silicon complementary metal-oxide semiconductor (CMOS) bulk-devices. A unified drain-current (Ⅰ-Ⅴ) model of SiNW incorporating velocity saturation effects is presented as an alternative approach in controlling the ultimate drift saturation and charge carrier mobility. Our results reveal that SiNWFET can significantly reduce drain-induced barrier lowering (DIBL) effect and subthreshold swing (SS) as well as provide a high on-off current ratio (I_(on)/I_(off)). The enhancement can be achieved by reducing the oxide thickness (T_(ox)) and increasing the diameter (T_(si)), channel length (L) and doping concentration (N_d). The investigation provides significant insight into the device performance of SiNWFET in electronic applications.