Inter-Modulation Linearity Investigation of an Optimally Designed and Optimally Biased LNA for Wireless LAN

摘要

This paper presents the effects of process parameters variations of new underlap SOI MOSFETs (underlap SOI technology with spacer covered) on linearity investigation of cascode low noise amplifier (LNA) for wireless LAN application. By quantifying the linearity of the LNA in-terms of third order intercept (IP3), the paper presents guidelines for optimum value of spacer s, film thickness T_(Si) doping gradient d and gate length L_G of the underlap device for linearity enhancement of the LNA. Based on a new Figure-of-Merit of LNA (FoM_(LNA)) involving available signal power gain G, IP3, noise figure (NF) and dc power consumption P_(dc), it has been found that FoM_(LNA) in double gate (DG) configuration is much higher than single gate (SG) one at the optimum gate overdrive V_(OD) = 75 mV. This is due to a combined effect of higher value of G and IP3 in the DG configuration. By comparing with limited available experimental data of 0.18 μm bulk technology, it has been found that using new underlap SOI MOSFETs with gate length of L_G = 60 nm (effective gate length L_(eff) = 92 nm) optimally designed and optimally biased LNA gives almost two times improvement in the proposed FoM_(LNA). With optimal bias the LNA achieved the following indicators: NF ～ 2.27 dB, IP3 ～ +7.75 dBm, G ～ 20.86 dB and power consumption equal to 2.5 mW.